8 Channel 12bit 250 MS/s Digitizer
Technical Specifications Table
Packaging 1-unit wide VME 6U module
Analog Input 8 channels, single-ended (SE) or differential.
Input range: 2 Vpp; Bandwidth: 125 MHz.
Programmable DAC for Offset Adjust x ch. (SE only).
Digital Conversion Resolution: 12 bit; Sampling rate: 10 to 250 MS/s simultaneously on each channel; multi board synchronization (one board can act as clock master).
External Gate Clock capability (NIM/TTL) for burst or single sampling mode.
ADC Sampling Clock generation Three operating modes:
- PLL mode - internal reference (50 MHz loc. oscillator).
- PLL mode - external reference on CLK_IN (Jitter<100ppm).
- PLL Bypass mode: Ext. clock on CLK_IN drives directly ADC clocks (Freq.: 10 250 MHz).
CLK_IN AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available using CAEN cable).
CLK_OUT DC coupled differential LVDS output clock, locked to ADC sampling clock. Freq.: 10 250MHz.
Memory Buffer 1.25 M sample/ch or 10 M sample/ch; Multi Event Buffer with independent read and write access. Programmable event size and pre-post trigger. Divisible into 1 1024 buffers.
Trigger Common External TRGIN (NIM or TTL) and VME CommandIndividual channel autotrigger (time over/under threshold)TRGOUT (NIM or TTL) for the trigger propagation to other V1720 boards.
Trigger Time Stamp 32bit – 8ns (34s range). Sync input for Time Stamp alignment
Optical Link Data readout and slow control with transfer rate up to 80 MB/s, to be used instead of VME bus. Daisy chainable: one A2818 PCI card can control and read eight V1720 boards in a chain.
VME interface VME64X compliant
D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast CyclesTransfer rate: 60MB/s (MBLT64), 100MB/s (2eVME), 160MB/s (2eSST).
Sequential and random access to the data of the Multi Event Buffer. The Chained readout allows to read one event from all the boards in a VME crate with a BLT access.
Upgrade V1720 firmware can be upgraded via VME or Optical Link
Software General purpose C Libraries and Demo Programs (CAENScope).
Analog Monitor 12bit / 100MHz DAC FPGA controlled output, four operating modes:
Test Waveform: 1 Vpp test ramp generator
Majority: MON/Σ output signal is proportional to the number of channels (enabled) under/over threshold (1 step = 125mV)
Buffer Occupancy: MON/Σ output signal is proportional to the Multi Event Buffer Occupancy
Voltage level: MON/Σ output signal is a programmable voltage level
LVDS I/O 16 gen. purpose LVDS I/O controlled by FPGA
Busy, Data Ready, Memory full, Individual Trig-Out and other function can be programmed.
An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker.
Input connectors Single ended: MCX
Differential: Tyco MODU II